rev 0.6 / nov. 2005 1 hy27us(08/16)281a series 128mbit (16mx8bit / 8m x16bit) nand flash document title 128mbit (16mx8bit / 8mx16bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. sep. 2004 preliminary 0.1 1) correct summary description & page.7 - the cache feature is deleted in summary description. - note.3 is deleted. (page.7) 2) correct table.5 & table.12 3) correct tsop1, wsop1 pin description - 38th pin has been changed lockpre 4) add bad block management & system interface using ce don?t care 5) change tsop1, wsop1, fbga package dimension & figures. - change tsop1, wsop1, fb ga package mechanical data - change tsop1, wsop1 package figures nov. 29. 2004 preliminary 0.2 1) lockpre is changed to pre. - texts, tables and figures are changed. 2) change command set - read a and b are changed to read 1. - read c is changed to read 2. 3) change ac, dc characterics - trb, tcry, tceh and toh are added. 4) correct program time (max) - before : 700us - after : 500us 5) edit figures - address names are changed. 6) change ac characterics mar. 03. 2005 preliminary trp trea before 30 35 after 25 30
rev 0.6 / nov. 2005 2 hy27us(08/16)281a series 128mbit (16mx8bit / 8m x16bit) nand flash revision history - continued - revision no. history draft date remark 0.3 1) change ac characteristics (1.8v device) 2) change ac parameter 3) add read id table 4) edit automatic read at power on & power on/off timing - texts & figure are changed. 5) insert the marking information. 6) change 128mb package type. - fbga package is deleted. - wsop package is chan ged to usop package. - figure & dimension are changed. jun. 13. 2005 preliminary 0.4 1) delete the 1.8v device?s features. 2 ) change ac conditions table 3 ) add tww parameter ( tww = 100ns, min) - texts & figures are added. - tww is added in ac timing characteristics table. 4) edit copy back program operation step 5) edit system interface using ce don?t care figures. 6) correct address cycle map. jul. 26. 2005 0.5 1) correct pkg dimension (tsop, usop pkg) sep. 02. 2005 0.6 1) correct usop figure. nov. 07. 2005 trc trp treh twc twp twh trea before 50 25 15 50 25 15 30 after 60 40 20 60 40 20 40 tcry(3.3v) tcry(1.8v) toh before 50+tr(r/b#) 50+tr(r/b#) 15 after 60+tr(r/b#) 60+tr(r/b#) 10 cp before 0.050 after 0.100
rev 0.6 / nov. 2005 3 hy27us(08/16)281a series 128mbit (16mx8bit / 8m x16bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 or x16 bus width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : hy27usxx281a memory cell array = (512+16) bytes x 32 pages x 1,024 blocks = (256+8) words x 32 pages x 1,024 blocks page size - x8 device : (512 + 16 spare) bytes : hy27us08281a - x16 device: (256 + 8 spare) words : HY27US16281A block size - x8 device: (16k + 512 spare) bytes - x16 device: (8k + 256 spare) words page read / program - random access: 10us (max.) - sequential access: 3.3v device: 50ns (min.) - page program time: 200us (typ.) copy back program mode - fast page copy without external buffering fast block erase - block erase time: 2ms (typ.) status register electronic signature - manufacturer code - device code chip enable don't care option - simple interface with microcontroller automatic page 0 read at power-up option - boot from nand support - automatic memory download serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles - 10 years data retention package - hy27us(08/16)281a-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27us(08/16)281a-t (lead) - hy27us(08/16)281a-tp (lead free) - hy27us(08/16)281a-s(p) : 48-pin usop1 (12 x 17 x 0.65 mm) - hy27us(08/16)281a-s (lead) - hy27us(08/16)281a-sp (lead free)
rev 0.6 / nov. 2005 4 hy27us(08/16)281a series 128mbit (16mx8bit / 8m x16bit) nand flash 1. summary description the hynix hy27us(08/16)281a series is a 16mx8bit with sp are 4g bit capacity. the device is offered in 1.8v vcc power supply and in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased indepe ndently so it is possible to preserve valid data while old data is erased. the device contains 1024 blocks, composed by 32 pages cons isting in two nand structures of 16 series connected flash cells. a program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 16k-byte(x8 device) block. data in the page mode can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. commands, data and addresses are synchronously in troduced using ce#, we#, ale and cle input pin. the on-chip program/erase controller automates all progra m and erase functions including pulse repetition, where required, and internal verifica tion and margining of data. the modifying can be locked using the wp# input pin. the output pin rb# (open drain buffer) signals the status of the device during each operat ion. in a system with mul- tiple memories the rb# pins can be connected al l together to provide a global status signal. even the write-intensive systems can take advantage of the hy27us(08/16)281a extended reliability of 100k program/ erase cycles by providing ecc (error correcting code) with real time mapping-out algorithm. optionally the chip could be offered with the ce# don?t care function. this option allows the direct download of the code from the nand flash memory device by a microcontrol ler, since the ce# transitions do not stop the read opera- tion. the copy back function allows the opti mization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section withou t the time consuming serial data insertion phase. this device includes also extra features like otp/unique id area, block lock mechanism, automatic read at power up, read id2 extension. the hynix hy27us(08/16)281a series is available in 48 - tsop1 12 x 20 mm, 48 - usop1 12 x 17 mm. 1.1 product list part number orization vcc range package hy27us08281a x8 2.7v - 3.6 volt 48tsop1/48usop1 HY27US16281A x16
rev 0.6 / nov. 2005 5 hy27us(08/16)281a series 128mbit (16mx8bit / 8m x16bit) nand flash 9 & |